package: glibc: Add optimization memory operations for RISCV
Port the memcpy & memset implementation from Linux kerenl to glibc to improve performance of memory operations in user space. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
This commit is contained in:
Mason Huo
+270
@@ -0,0 +1,270 @@
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From 15850d406a9807d70e752aacfbb456946a01f6ac Mon Sep 17 00:00:00 2001
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From: Mason Huo <mason.huo@starfivetech.com>
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Date: Tue, 21 Mar 2023 14:36:21 +0800
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Subject: [PATCH] Optimize memory operations for RISCV
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Port the memcpy & memset implementation from
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Linux kerenl to glibc to improve performance of
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memory operations in user space.
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---
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sysdeps/riscv/memcpy.S | 120 +++++++++++++++++++++++++++++++++++++++++
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sysdeps/riscv/memset.S | 120 +++++++++++++++++++++++++++++++++++++++++
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2 files changed, 240 insertions(+)
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create mode 100644 sysdeps/riscv/memcpy.S
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create mode 100644 sysdeps/riscv/memset.S
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diff --git a/sysdeps/riscv/memcpy.S b/sysdeps/riscv/memcpy.S
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new file mode 100644
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index 00000000..aa0eaee9
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--- /dev/null
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+++ b/sysdeps/riscv/memcpy.S
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@@ -0,0 +1,120 @@
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+/* memcpy for RISC-V.
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+ Copyright (C) 1996-2020 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library. If not, see
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+ <https://www.gnu.org/licenses/>. */
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+
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+#include <sysdep.h>
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+#include <sys/asm.h>
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+
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+ENTRY(memcpy)
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+ move t6, a0 /* Preserve return value */
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+
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+ /* Defer to byte-oriented copy for small sizes */
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+ sltiu a3, a2, 128
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+ bnez a3, 4f
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+ /* Use word-oriented copy only if low-order bits match */
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+ andi a3, t6, SZREG-1
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+ andi a4, a1, SZREG-1
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+ bne a3, a4, 4f
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+
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+ beqz a3, 2f /* Skip if already aligned */
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+ /*
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+ * Round to nearest double word-aligned address
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+ * greater than or equal to start address
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+ */
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+ andi a3, a1, ~(SZREG-1)
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+ addi a3, a3, SZREG
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+ /* Handle initial misalignment */
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+ sub a4, a3, a1
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+1:
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+ lb a5, 0(a1)
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+ addi a1, a1, 1
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+ sb a5, 0(t6)
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+ addi t6, t6, 1
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+ bltu a1, a3, 1b
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+ sub a2, a2, a4 /* Update count */
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+
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+2:
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+ andi a4, a2, ~((16*SZREG)-1)
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+ beqz a4, 4f
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+ add a3, a1, a4
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+3:
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+ REG_L a4, 0(a1)
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+ REG_L a5, SZREG(a1)
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+ REG_L a6, 2*SZREG(a1)
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+ REG_L a7, 3*SZREG(a1)
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+ REG_L t0, 4*SZREG(a1)
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+ REG_L t1, 5*SZREG(a1)
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+ REG_L t2, 6*SZREG(a1)
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+ REG_L t3, 7*SZREG(a1)
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+ REG_L t4, 8*SZREG(a1)
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+ REG_L t5, 9*SZREG(a1)
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+ REG_S a4, 0(t6)
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+ REG_S a5, SZREG(t6)
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+ REG_S a6, 2*SZREG(t6)
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+ REG_S a7, 3*SZREG(t6)
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+ REG_S t0, 4*SZREG(t6)
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+ REG_S t1, 5*SZREG(t6)
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+ REG_S t2, 6*SZREG(t6)
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+ REG_S t3, 7*SZREG(t6)
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+ REG_S t4, 8*SZREG(t6)
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+ REG_S t5, 9*SZREG(t6)
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+ REG_L a4, 10*SZREG(a1)
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+ REG_L a5, 11*SZREG(a1)
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+ REG_L a6, 12*SZREG(a1)
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+ REG_L a7, 13*SZREG(a1)
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+ REG_L t0, 14*SZREG(a1)
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+ REG_L t1, 15*SZREG(a1)
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+ addi a1, a1, 16*SZREG
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+ REG_S a4, 10*SZREG(t6)
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+ REG_S a5, 11*SZREG(t6)
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+ REG_S a6, 12*SZREG(t6)
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+ REG_S a7, 13*SZREG(t6)
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+ REG_S t0, 14*SZREG(t6)
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+ REG_S t1, 15*SZREG(t6)
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+ addi t6, t6, 16*SZREG
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+ bltu a1, a3, 3b
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+ andi a2, a2, (16*SZREG)-1 /* Update count */
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+
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+4:
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+ /* Handle trailing misalignment */
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+ beqz a2, 6f
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+ add a3, a1, a2
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+
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+ /* Use word-oriented copy if co-aligned to word boundary */
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+ or a5, a1, t6
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+ or a5, a5, a3
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+ andi a5, a5, 3
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+ bnez a5, 5f
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+7:
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+ lw a4, 0(a1)
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+ addi a1, a1, 4
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+ sw a4, 0(t6)
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+ addi t6, t6, 4
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+ bltu a1, a3, 7b
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+
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+ ret
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+
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+5:
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+ lb a4, 0(a1)
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+ addi a1, a1, 1
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+ sb a4, 0(t6)
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+ addi t6, t6, 1
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+ bltu a1, a3, 5b
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+6:
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+ ret
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+END(memcpy)
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+libc_hidden_builtin_def (memcpy)
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diff --git a/sysdeps/riscv/memset.S b/sysdeps/riscv/memset.S
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new file mode 100644
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index 00000000..431a19f5
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--- /dev/null
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+++ b/sysdeps/riscv/memset.S
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@@ -0,0 +1,120 @@
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+/* memset for RISC-V.
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+ Copyright (C) 1996-2020 Free Software Foundation, Inc.
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+ This file is part of the GNU C Library.
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+
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+ The GNU C Library is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU Lesser General Public
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+ License as published by the Free Software Foundation; either
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+ version 2.1 of the License, or (at your option) any later version.
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+
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+ The GNU C Library is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ Lesser General Public License for more details.
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+
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+ You should have received a copy of the GNU Lesser General Public
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+ License along with the GNU C Library. If not, see
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+ <https://www.gnu.org/licenses/>. */
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+
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+#include <sysdep.h>
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+#include <sys/asm.h>
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+
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+ENTRY(memset)
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+ move t0, a0 /* Preserve return value */
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+
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+ /* Defer to byte-oriented fill for small sizes */
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+ sltiu a3, a2, 16
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+ bnez a3, 4f
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+
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+ /*
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+ * Round to nearest XLEN-aligned address
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+ * greater than or equal to start address
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+ */
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+ addi a3, t0, SZREG-1
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+ andi a3, a3, ~(SZREG-1)
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+ beq a3, t0, 2f /* Skip if already aligned */
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+ /* Handle initial misalignment */
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+ sub a4, a3, t0
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+1:
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+ sb a1, 0(t0)
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+ addi t0, t0, 1
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+ bltu t0, a3, 1b
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+ sub a2, a2, a4 /* Update count */
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+
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+2: /* Duff's device with 32 XLEN stores per iteration */
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+ /* Broadcast value into all bytes */
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+ andi a1, a1, 0xff
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+ slli a3, a1, 8
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+ or a1, a3, a1
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+ slli a3, a1, 16
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+ or a1, a3, a1
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+ slli a3, a1, 32
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+ or a1, a3, a1
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+
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+ /* Calculate end address */
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+ andi a4, a2, ~(SZREG-1)
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+ add a3, t0, a4
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+
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+ andi a4, a4, 31*SZREG /* Calculate remainder */
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+ beqz a4, 3f /* Shortcut if no remainder */
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+ neg a4, a4
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+ addi a4, a4, 32*SZREG /* Calculate initial offset */
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+
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+ /* Adjust start address with offset */
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+ sub t0, t0, a4
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+
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+ /* Jump into loop body */
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+ /* Assumes 32-bit instruction lengths */
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+ la a5, 3f
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+ srli a4, a4, 1
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+ add a5, a5, a4
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+ jr a5
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+3:
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+ REG_S a1, 0(t0)
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+ REG_S a1, SZREG(t0)
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+ REG_S a1, 2*SZREG(t0)
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+ REG_S a1, 3*SZREG(t0)
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+ REG_S a1, 4*SZREG(t0)
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+ REG_S a1, 5*SZREG(t0)
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+ REG_S a1, 6*SZREG(t0)
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+ REG_S a1, 7*SZREG(t0)
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+ REG_S a1, 8*SZREG(t0)
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+ REG_S a1, 9*SZREG(t0)
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+ REG_S a1, 10*SZREG(t0)
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+ REG_S a1, 11*SZREG(t0)
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+ REG_S a1, 12*SZREG(t0)
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+ REG_S a1, 13*SZREG(t0)
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+ REG_S a1, 14*SZREG(t0)
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+ REG_S a1, 15*SZREG(t0)
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+ REG_S a1, 16*SZREG(t0)
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+ REG_S a1, 17*SZREG(t0)
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+ REG_S a1, 18*SZREG(t0)
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+ REG_S a1, 19*SZREG(t0)
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+ REG_S a1, 20*SZREG(t0)
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+ REG_S a1, 21*SZREG(t0)
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+ REG_S a1, 22*SZREG(t0)
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+ REG_S a1, 23*SZREG(t0)
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+ REG_S a1, 24*SZREG(t0)
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+ REG_S a1, 25*SZREG(t0)
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+ REG_S a1, 26*SZREG(t0)
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+ REG_S a1, 27*SZREG(t0)
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+ REG_S a1, 28*SZREG(t0)
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+ REG_S a1, 29*SZREG(t0)
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+ REG_S a1, 30*SZREG(t0)
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+ REG_S a1, 31*SZREG(t0)
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+ addi t0, t0, 32*SZREG
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+ bltu t0, a3, 3b
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+ andi a2, a2, SZREG-1 /* Update count */
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+
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+4:
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+ /* Handle trailing misalignment */
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+ beqz a2, 6f
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+ add a3, t0, a2
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+5:
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+ sb a1, 0(t0)
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+ addi t0, t0, 1
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+ bltu t0, a3, 5b
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+6:
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+ ret
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+END(memset)
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+libc_hidden_builtin_def (memset)
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--
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2.39.2
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