Merge branch 'CR_1140_v4l2_test_changhuang.liang' into 'jh7110-devel'

v4l2test: add pipeline_setting dphy->csi2rx->wr See merge request sdk/buildroot!8
2022-06-08 04:27:49 +00:00
parent 9b9c7d7095 d210292dfc
commit 313e975390
1 changed files with 4 additions and 0 deletions
@@ -98,6 +98,8 @@ case $1 in
 				case $2 in
 					VIN)
 						echo "csiphy0 CSIRX0 vin 使能pipeline:"
+						media-ctl -vl "'stf_csiphy0':1 -> 'stf_csi0':0 [1]"
+						media-ctl -vl "'stf_csi0':1 -> 'stf_vin0_wr':0 [1]"
 						;;
 					ISP0)
 						echo "csiphy0 CSIRX0 ISP0 使能pipeline:"
@@ -139,6 +141,8 @@ case $1 in
 				case $2 in
 					VIN)
 						echo "csiphy0 CSIRX0 vin 关闭pipeline:"
+						media-ctl -vl "'stf_csiphy0':1 -> 'stf_csi0':0 [0]"
+						media-ctl -vl "'stf_csi0':1 -> 'stf_vin0_wr':0 [0]"
 						;;
 					ISP0)
 						echo "csiphy0 CSIRX0 ISP0 关闭pipeline:"