From ec4c0b5e652ce1080c72e9f527af6c586925ba6f Mon Sep 17 00:00:00 2001
From: Andy Hu <andy.hu@starfivetech.com>
Date: Wed, 12 Jul 2023 12:29:11 +0800
Subject: [PATCH 1/2] add riscv support

---
 Source/JavaScriptCore/CMakeLists.txt |  1 +
 Source/WTF/wtf/Platform.h            | 12 ++++++++++--
 Source/WTF/wtf/dtoa/utils.h          |  6 +++---
 3 files changed, 14 insertions(+), 5 deletions(-)
 mode change 100644 => 100755 Source/JavaScriptCore/CMakeLists.txt
 mode change 100644 => 100755 Source/WTF/wtf/Platform.h
 mode change 100644 => 100755 Source/WTF/wtf/dtoa/utils.h

diff --git a/Source/JavaScriptCore/CMakeLists.txt b/Source/JavaScriptCore/CMakeLists.txt
old mode 100644
new mode 100755
index 73917eb5..479b7d3c
--- a/Source/JavaScriptCore/CMakeLists.txt
+++ b/Source/JavaScriptCore/CMakeLists.txt
@@ -535,6 +535,7 @@ if (WTF_CPU_ARM)
 
         list(APPEND JavaScriptCore_SOURCES ${DERIVED_SOURCES_DIR}/GeneratedJITStubs.obj)
     endif ()
+elseif (WTF_CPU_RISCV64)
 elseif (WTF_CPU_MIPS)
 elseif (WTF_CPU_X86)
 elseif (WTF_CPU_X86_64)
diff --git a/Source/WTF/wtf/Platform.h b/Source/WTF/wtf/Platform.h
old mode 100644
new mode 100755
index 9cf65684..e3956824
--- a/Source/WTF/wtf/Platform.h
+++ b/Source/WTF/wtf/Platform.h
@@ -357,7 +357,14 @@
 #endif
 #endif
 
-#if CPU(ARM) || CPU(MIPS) || CPU(SH4) || CPU(SPARC) || CPU(MIPS64)
+#if defined(__riscv)
+#define WTF_CPU_RISCV 1
+#if __riscv_xlen == 64
+#define WTF_CPU_RISCV64 1
+#endif
+#endif
+
+#if CPU(ARM) || CPU(MIPS) || CPU(SH4) || CPU(SPARC) || CPU(MIPS64) || CPU(RISCV)
 #define WTF_CPU_NEEDS_ALIGNED_ACCESS 1
 #endif
 
@@ -761,7 +768,8 @@
     || CPU(S390X) \
     || CPU(AARCH64) \
     || CPU(MIPS64) \
-    || CPU(PPC64)
+    || CPU(PPC64) \
+    || CPU(RISCV64)
 #define WTF_USE_JSVALUE64 1
 #else
 #define WTF_USE_JSVALUE32_64 1
diff --git a/Source/WTF/wtf/dtoa/utils.h b/Source/WTF/wtf/dtoa/utils.h
old mode 100644
new mode 100755
index 298bf4d9..07032773
--- a/Source/WTF/wtf/dtoa/utils.h
+++ b/Source/WTF/wtf/dtoa/utils.h
@@ -49,7 +49,7 @@
 defined(__ARMEL__) || \
 defined(_MIPS_ARCH_MIPS32R2)
 #define DOUBLE_CONVERSION_CORRECT_DOUBLE_OPERATIONS 1
-#elif CPU(MIPS) || CPU(PPC) || CPU(PPC64) || OS(WINCE) || CPU(SH4) || CPU(S390) || CPU(S390X) || CPU(IA64) || CPU(SPARC) || CPU(ALPHA) || CPU(MIPS64) || CPU(AARCH64) || CPU(HPPA)
+#elif CPU(MIPS) || CPU(PPC) || CPU(PPC64) || OS(WINCE) || CPU(SH4) || CPU(S390) || CPU(S390X) || CPU(IA64) || CPU(SPARC) || CPU(ALPHA) || CPU(MIPS64) || CPU(AARCH64) || CPU(HPPA) || CPU(RISCV)
 #define DOUBLE_CONVERSION_CORRECT_DOUBLE_OPERATIONS 1
 #elif defined(_M_IX86) || defined(__i386__)
 #if defined(_WIN32)
@@ -151,7 +151,7 @@ namespace double_conversion {
         // spanning from and including 'from', to but not including 'to'.
         BufferReference<T> SubBufferReference(int from, int to) {
             ASSERT(to <= length_);
-            ASSERT(from < to);
+            ASSERT_WITH_SECURITY_IMPLICATION(from < to);
             ASSERT(0 <= from);
             return BufferReference<T>(start() + from, to - from);
         }
@@ -292,7 +292,7 @@ namespace double_conversion {
     inline Dest BitCast(const Source& source) {
         // Compile time assertion: sizeof(Dest) == sizeof(Source)
         // A compile error here means your Dest and Source have different sizes.
-        typedef char VerifySizesAreEqual[sizeof(Dest) == sizeof(Source) ? 1 : -1];
+        static_assert(sizeof(Dest) == sizeof(Source), "Source and destination sizes must be equal");
         
         Dest dest;
         memcpy(&dest, &source, sizeof(dest));
-- 
2.41.0