From d210292dfc10771366dedc0cac12561255007138 Mon Sep 17 00:00:00 2001 From: "changhuang.liang" Date: Wed, 8 Jun 2022 10:41:31 +0800 Subject: [PATCH] v4l2test: add pipeline_setting dphy->csi2rx->wr Signed-off-by: changhuang.liang --- package/v4l2_test/pipeline_setting.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/package/v4l2_test/pipeline_setting.sh b/package/v4l2_test/pipeline_setting.sh index 89780686..b7f03d1e 100755 --- a/package/v4l2_test/pipeline_setting.sh +++ b/package/v4l2_test/pipeline_setting.sh @@ -98,6 +98,8 @@ case $1 in case $2 in VIN) echo "csiphy0 CSIRX0 vin 使能pipeline:" + media-ctl -vl "'stf_csiphy0':1 -> 'stf_csi0':0 [1]" + media-ctl -vl "'stf_csi0':1 -> 'stf_vin0_wr':0 [1]" ;; ISP0) echo "csiphy0 CSIRX0 ISP0 使能pipeline:" @@ -139,6 +141,8 @@ case $1 in case $2 in VIN) echo "csiphy0 CSIRX0 vin 关闭pipeline:" + media-ctl -vl "'stf_csiphy0':1 -> 'stf_csi0':0 [0]" + media-ctl -vl "'stf_csi0':1 -> 'stf_vin0_wr':0 [0]" ;; ISP0) echo "csiphy0 CSIRX0 ISP0 关闭pipeline:"