diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index f3bf2b34..8d223614 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -27,4 +27,13 @@ ifeq ($(BR2_RISCV_ISA_RVC),y)
 GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
 endif
 
+# Starting from gcc 12.x, csr and fence instructions have been
+# separated from the base I instruction set, and special -march
+# suffixes are needed to enable their support. In Buildroot, we assume
+# all RISC-V cores that support Linux implement those instructions, so
+# we unconditionally enable those extensions.
+ifeq ($(BR2_TOOLCHAIN_GCC_AT_LEAST_12),y)
+GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei
+endif
+
 endif